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Altera_Forum
Honored Contributor
Honored ContributorTiming Constraint problem on set_input_delay
Hello. I have encountered problems on the following timing constraint. The case is draw in the attachment. I do timing constraint as follows. creat_generated_clock -add -name {SysClk} -sourc...
Altera_ForumHonored Contributor
Honored ContributorHey Rysc,
In that example you gave using number 2. How do you figure out the period for the virtual clock? Say for example I have a flash memory bust (address and data lines and control lines) I need to constrain. If I constrain them to a virtual clock period how would I go about figuring out what that period needs to be?
