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Altera_Forum
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12 years ago

Timing Constraint problem on set_input_delay

Hello. I have encountered problems on the following timing constraint. The case is draw in the attachment. I do timing constraint as follows. creat_generated_clock -add -name {SysClk} -sourc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thank you!It is very helpful.

I had no idea to remove the warning "No paths exist between clock target "A[0]" of clock "A0_Clk" and its clock source. Assuming zero source clock latency.".

And you are right,it is very ugly.I will use option 2.