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Altera_Forum
Honored Contributor
Honored ContributorTiming Constraint problem on set_input_delay
Hello. I have encountered problems on the following timing constraint. The case is draw in the attachment. I do timing constraint as follows. creat_generated_clock -add -name {SysClk} -sourc...
Altera_ForumHonored Contributor
Honored ContributorI have tried my best to find out what has gone wrong.And still I don't known what goes wrong.I have attached the project.Could you help me to find out the problem?
