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Altera_Forum
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12 years ago

Timing Constraint problem on set_input_delay

Hello. I have encountered problems on the following timing constraint. The case is draw in the attachment. I do timing constraint as follows. creat_generated_clock -add -name {SysClk} -sourc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Option 2 is much more like constraining two FPGAs talking to each other, whereby you have to just constrain one side to what it can do(I find the output side easiest) and then feed that information to the input side.

On your last comment, the datapath certainly needs to be in the calculation, so something went wrong.