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XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Timing constraint for clock divided by timer

Hello, I am doing timing constraint for serial adc ic as below verilog code. clk below comes from system clock from a pll, and divide clock by 250 through timer. Question 1) :so I define adc_scl...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY