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Occasional Contributor

5 years ago

Timing constraint for clock divided by timer

Hello, I am doing timing constraint for serial adc ic as below verilog code. clk below comes from system clock from a pll, and divide clock by 250 through timer. Question 1) :so I define adc_scl...

KhaiChein_Y_Intel

Regular Contributor

5 years ago

Hi,

You have to constrain the signals:

Clock - create_clock

PLL - create_generated_clock or derive_pll_clock

adc_sclk - create_generated_clock

adc_data - set_input_delay

adc_sc - set_output_delay, false path and multicycle constraints depending on your design. You may refer to this document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf

Thanks

Best regards,

KhaiY

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Timing constraint for clock divided by timer

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