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Altera_Forum's avatar
Altera_Forum
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13 years ago

Timing Closure issue in Stratix V

Device: 5SGSMD8K3F40I3

My design consists of niosii core with one ITCM (32 Kbytes) and one DTCM (16 Kbytes).

Its difficult to close timings for the design. The reference clock is 245 MHz.

There are a few setup (TNS = -0.201 nsec) and recovery violations (TNS = -0.221 nsec) inside the NIOSII which is third party IP with no control to modify the recovery or setup paths.

Any idea of how to improve the setup and recovery timings...?

Thanks,

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    If your system is in SOPC, you might try adding pipeline bridges into your design. Other than that, you may try running some of the parts at a slower rate and using a clock crossing bridge. (245MHz does seem a bit fast)

    I have not worked with Q-Sys at all, so I don't know if the design flow uses the same blocks.