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Honored Contributor
Honored ContributorTiming Closure issue in Stratix V
Device: 5SGSMD8K3F40I3 My design consists of niosii core with one ITCM (32 Kbytes) and one DTCM (16 Kbytes). Its difficult to close timings for the design. The reference clock is 245 MHz. The...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Device: 5SGSMD8K3F40I3 The reference clock is 245 MHz. --- Quote End --- Not sure if nios can be implemented with this clock. http://www.altera.com/literature/hb/nios2/n2cpu_nii51015.pdf
