Forum Discussion

AlexShepel's avatar
AlexShepel
Icon for New Contributor rankNew Contributor
5 years ago

Timing analysis for separate HDL modules

We always have some HDL modules that are used in different FPGA projects. It may be a DSP module or protocol controller, etc. It is a good practice to design modules that can be reused. We...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

We do not receive any response from you to the previous reply, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.