Timing analysis for separate HDL modules

We always have some HDL modules that are used in different FPGA projects. It may be a DSP module or protocol controller, etc. It is a good practice to design modules that can be reused.

We think about an HDL module as a finite structure. It makes us keep in mind some significant timing analysis questions. What will be the Fmax? Where we must place registers to achieve uniform register-to-register timings?

Getting answers brings us benefits. We design modules that will be easily configurable for future projects. We avoid changes in the HDL code. For example, we can simply specify Fmax as a comment below the module description. Rough slow corner estimation is enough.

//  Name	    :   multiplexer
//  Author	    :   Alex Shepel
//  Description	:   Multiplexes input signals. 
//                  Selects channel by binary number on "sel" bus.                    
//  Fmax	    :   10M50SCE144I7G  =  250 MHz
//		            10M50SCE144I6G  =  300 MHz

So we need post-map timing analysis for separate modules. In this case, we must write SDC constraints for them. And here I have trouble. What data input delay we choose? I think we must imagine our module as part of some abstract project. Assume that data comes to the module input ports at the perfect timing (as it is synchronized).

What are these timings? At least, they must cover the setup time of the flip-flop. But where can I find this value? It will be great to receive a link to the datasheet. Unfortunately, I can’t find these timings by myself for the Max10 family.

Also, it will be great to receive other recommendations for post-map timing analysis of separate HDL modules. Maybe I have mistakes in my question or such timing analysis is meaningless. It will be great to see such thoughts too.