TimeQuest Timing Analyzer

That might be the fastest this path can go. In general you should try and constrain with your create_clock, set_input_delay, set_output_delay, and multicycle type commands and try and avoid drilling down to individual nets as constraints. If you describe why you want to use the set_net_delay constraint we might be able to suggest another way to constrain your overall path.

From the "set_net_delay" description http://quartushelp.altera.com/14.1/mergedprojects/tafs/tafs/tcl_pkg_sdc_ext_ver_1.0_cmd_set_net_delay.htm, it is actually not a "constraint" and just provides a report to the specified path according to the your requirement. After being applied, you can find the report in "Report Net Delay" in TimeQuest. To constraint the data path, you can consider using "set_max_delay" http://quartushelp.altera.com/14.1/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_set_max_delay.htm