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Cliver1's avatar
Cliver1
Icon for New Contributor rankNew Contributor
3 years ago
Solved

TimeQuest report timing finds 2 paths inside the Cyclone 2 FPGA for the same design path

Hello, when I analyse the path from P1_EnergyMonAInClk40m[6] to P1_PeakPowerClk40m[6] for example in my design using Report Timing in TimeQuest 2 paths are reported with different timing delays. The ...
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  • Cliver1's avatar
    Cliver1
    3 years ago

    False alarm. There are 2 possible data paths in my design!

SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

I now transition this thread to community support. If you have a new question, Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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