TimeQuest Ignoring create_generated_clock for SPI Clock Derived from Gated Divide-by-4 Signal (sck_r

The output of a PLL should be a generated clock, not create_clock. Depending on your target device, you may need to include derive_pll_clocks to specify the output generated clocks from the PLL. If it's Stratix 10 or Agilex, you don't have to issue this command and you should remove the constraint for outclk_0. Does outclk_0 appear in report_clocks?

Since you are using a PLL anyway, why aren't you just generating sck from that instead of building a divider?

Your -source should point to the output pin of the PLL (get_pins) to guarantee the correct reference is used as the source.

Also, you named both generated clocks the same in your .sdc. They can't both be sck.