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Dear All,
is it possible to use generic of type 'time' in an entity declaration which is used for synthesis? I'd like to use time specification as top-entity generic parameter, which is in the sub-entity recalculated to integer and hence it is fully synthesizable (recalculation using e.g. 100 ns / 25 ns leads to integer right?).
This works great in simulation, however quartus refuses to instantiate block claiming that 's' does not exist:
entity top_entity is
generic (
DELAY_LINE_DEPTH : integer := 8; --! default FIFO used for BLR
RESET_PULSE_LENGTH : integer := 50; --! length of automatically generated reset
BCF_DEFAULT_THRESHOLD_VALUE : integer := 3700; --! default value of threshold loaded when register is reset
MAX6627_AUTORUN : time := 2s); --! autorun of max circuit
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Hi,
I'm not a VHDL expert, but what would you like to achieve ? Should your design run for a certain time ?
King regards
GPK
Honored Contributor
