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Altera_Forum's avatar
Altera_Forum
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14 years ago

This noob needs help...

Hello everyone,

I've recently started using ModelSim Altera Starter Edition 10.0c and I'm trying to get simulate a really simple "AND" gate. Here's my code: 

library ieee;
use ieee.std_logic_1164.all;
entity mygate is
  port( x,y : in std_logic;
          z     : out std_logic);
end entity mygate;
architecture here of mygate is
begin
z <= (x and y);
end architecture here;

It compiles fine but I have no clue how to set boolean values to x and y and run the simulation. I've been trying for the last few hours and I'm completely lost. Please help.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    you need to create a testbench - this is another VHDL entity that instantiates your and gate and sets the input values. It does not have to be synthesisable - something like this: 

    
library ieee;
use ieee.std_logic_1164.all;
entity mygate_TB is
end entity mygate_TB;
  
architecture RTL of mtgate_TB is
  signal x,y,z : std_logic;
begin
  
  UUT : entity work.mygate;
  port map (
    x => x,
    y => y,
    z => z    
  )
  
  x <= '0', '1' after 100 ns, '0' after 200 ns;
  y <= '1',                   '0' after 300 ns;  
  
end architecture RTL;
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I've tried this code as an additional vhdl file to he original one i posted: 

    library ieee; 
use ieee.std_logic_1164.all;  
entity mygate_TB is 
end entity mygate_TB;   
 
architecture RTL of mygate_TB is   
signal x,y,z : std_logic; 
begin      
UUT : entity work.mygate;   
port map (     
x => x,     
y => y,     
z => z       
)      
x <= '0', '1' after 100 ns, '0' after 200 ns;   
y <= '1',                   '0' after 300 ns;  
    
end architecture RTL;
    I've corrected the "mygate_TB" problem and get this error when compiling: 

    vcom -work work -2002 -explicit C:/altera/11.1/modelsim_ase/test.vhd
Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mygate_TB
-- Compiling architecture RTL of mygate_TB
-- Loading entity mygate
** Error: C:/altera/11.1/modelsim_ase/test.vhd(11): (vcom-1035) Formal port "x" has OPEN or no actual associated with it.
** Error: C:/altera/11.1/modelsim_ase/test.vhd(11): (vcom-1035) Formal port "y" has OPEN or no actual associated with it.
** Error: C:/altera/11.1/modelsim_ase/test.vhd(12): near "port": syntax error
** Error: C:/altera/11.1/modelsim_ase/test.vhd(21): VHDL Compiler exiting
    Hmmm... what's going on? I don't understand what the "UUT" part means. I'm just looking for a simple simlulation which will test the gate.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    oops, remove the semicolon from the end of the UUT line, and put one at the end of the port map.

    The UUT is just a name given to the instantiated entity. IT can be any identifier you want - UUT standard for unit under test.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks. Everything compiles ok. But how do I run the simulation now? I tried adding the objects x, y, and z to the wave graph but their values are just described as "U"...

    never mind I got it. thanks.

    One last thing... all my windows are filling up the whole screen, but I would prefer to have them all take up less space so I can see more than one window at once. For example I want to see the project tab and mygate.vhd tab at once on the screen. How do I do this?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You can detatch any of the windows and move them around as you want. Otherwise just get another monitor unfortunately.