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Altera_Forum's avatar
Altera_Forum
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14 years ago

This noob needs help...

Hello everyone, I've recently started using ModelSim Altera Starter Edition 10.0c and I'm trying to get simulate a really simple "AND" gate. Here's my code: library ieee; use ieee.std_l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

you need to create a testbench - this is another VHDL entity that instantiates your and gate and sets the input values. It does not have to be synthesisable - something like this: 


library ieee;
use ieee.std_logic_1164.all;
entity mygate_TB is
end entity mygate_TB;
  
architecture RTL of mtgate_TB is
  signal x,y,z : std_logic;
begin
  
  UUT : entity work.mygate;
  port map (
    x => x,
    y => y,
    z => z    
  )
  
  x <= '0', '1' after 100 ns, '0' after 200 ns;
  y <= '1',                   '0' after 300 ns;  
  
end architecture RTL;