This noob needs help...

you need to create a testbench - this is another VHDL entity that instantiates your and gate and sets the input values. It does not have to be synthesisable - something like this:

library ieee;
use ieee.std_logic_1164.all;
entity mygate_TB is
end entity mygate_TB;
  
architecture RTL of mtgate_TB is
  signal x,y,z : std_logic;
begin
  
  UUT : entity work.mygate;
  port map (
    x => x,
    y => y,
    z => z    
  )
  
  x <= '0', '1' after 100 ns, '0' after 200 ns;
  y <= '1',                   '0' after 300 ns;  
  
end architecture RTL;