The virtual clock about input or output in timing constrain

When we do timing constrain in input or output, usually we need create a virtual clock. My question is, how can I know the phase relation between virtual clock and clock inside the system, in order to define virtual clock?

Another question is similar, if in my design, one FPGA input is drive by another FPGA output. But the input and output are drive by two different clock source with same parameters (same model oscillations). How can I know these two clock sources phase relation in order to define these two virtual clocks in timing constrain?

Thanks very much.