Forum Discussion
EBoln
Occasional Contributor
Occasional ContributorThe problem with two external PLL for LVDS RX
I have two identical interfaces: Deserialization factor: 8 Channels: 8 Clock: 50MHz If I implement only one interface, then everything is fine. However, after adding the second implementation, I ...
BJonaOccasional Contributor
Occasional Contributoryou can only have one PLL for one bank.
