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Honored Contributor

8 years ago

The problem for using DPA PLL

Hi, for my project, I need receive 5 channels 500M LVDS sigal and with 50M sync following clock, I add a PLL for every following clock and generate 50M Phase342, 500M Phase180, 50M Phase288 D...

Altera_Forum

Honored Contributor

8 years ago

Could you list out the PLLs, the config of each PLL , inputs to each and outputs. I need to get a clear picture. Are the PLLs connected to global GCLK pins in FPGA?

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The problem for using DPA PLL

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