Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorThe problem for using DPA PLL
Hi, for my project, I need receive 5 channels 500M LVDS sigal and with 50M sync following clock, I add a PLL for every following clock and generate 50M Phase342, 500M Phase180, 50M Phase288 D...
Altera_ForumHonored Contributor
Honored ContributorCould you list out the PLLs, the config of each PLL , inputs to each and outputs. I need to get a clear picture. Are the PLLs connected to global GCLK pins in FPGA?
