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Altera_Forum's avatar
Altera_Forum
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8 years ago

The problem for using DPA PLL

Hi, for my project, I need receive 5 channels 500M LVDS sigal and with 50M sync following clock, I add a PLL for every following clock and generate 50M Phase342, 500M Phase180, 50M Phase288 D...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Use the clock control block on the PLL that is not having DPA. Drive the other 5 PLL inputs directly from the FPGA pin.