--- Quote Start ---
The issue is not related to the PLL outputs, but rather the input to the fractional PLL. When using fractional PLLs the input clock to the PLL should not be driven directly from the Clock pin. You should insert a Clock control block between the FPGA clock input pin and the PLL as shown below:
https://alteraforum.com/forum/attachment.php?attachmentid=14487&stc=1 Also check which PLL is the one affected. You may need to use the clock control for PLLs that do not connect to DPA blocks. for ones that connect to DPA, the PLL should be driven directly from the Clock input pin of the FPGA.
--- Quote End ---
Thanks for support. actually now, i need five LVDS following clk input connected to the PLL with the DPA function. only the osc input one for system using do not need DPA function.
Totally six pll, five of them with DPA function and one without DPA.
Honored Contributor
