The Fitter failed to find a legal placement for IOPLL with DIB of Stratix 10.

Hi Or,

Have you check this guideline?

https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/clocking-in-asynchronous-and-synchronous.html

It mentioned that "the DIB subsystem sends a source synchronous clock to another DIB subsystem in the adjacent die (TX or RX). In Synchronous mode, the system clock is synchronous to the DIB clock."

Regards,

Aqid