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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

The Fitter failed to find a legal placement for IOPLL with DIB of Stratix 10.

I got the next Error from the Fitter while trying to synthesis with DIB The Fitter Failed to find legal placement for my IOPLL is there a way to find out which PLL is preferred by the DIB , or ...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Or,


Apologies as I am did not aware that clocks are being transferred to another die via DIB.


Have you tried to provide the input clock signal to the IOPLL through dedicated clock pins?


Regards,

Aqid


OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I didn't try because my design is Source-synchronous , clock is coming WITH the data.

it seems that Intel does not support "Source-synchronous" via DIB and it is not written any where ...

Or.