i am working with EPM570T100I5,which has no PLL,i want to get a 1MHz clcok,the global clock is 50MHz.i have read the posts about clcok divider,the enable clock is a good way,but i am a newbie,i didnot kown what to do,can anybody give me a hand,thx a lot!!

Hi, use a counter running continuously on your 50MHz clk from 0 to 49 and back. generate a single enable pulse when count say = 49. Enable should be low otherwise. Then use this enable pulse together with your 50MHz clk to enable your work at 1MHz. Additionally, you may add a multicycle of 50 to your logic timing constraints since the required speed is now just 1MHz. Obviously, you don't need to do this if your design doesn't violate the 50MHz. Regards kaz

--- Quote Start --- Hi, use a counter running continuously on your 50MHz clk from 0 to 49 and back. generate a single enable pulse when count say = 49. Enable should be low otherwise. Then use this enable pulse together with your 50MHz clk to enable your work at 1MHz. Additionally, you may add a multicycle of 50 to your logic timing constraints since the required speed is now just 1MHz. Obviously, you don't need to do this if your design doesn't violate the 50MHz. Regards kaz --- Quote End --- In accordance with your post, I wrote the following code,could tell me is it right?is it the enable clock divider? THX very much. module divider (clk, rst_n, clk_o); parameter TIMECONST_49 = 6'b110001; input clk; input rst_n; output reg clk_o; reg [5:0] div_50; reg en_50; always @ (posedge clk or negedge rst_n) begin if (!rst_n) begin div_50 <= 6'b000000; en_50 <= 1'b0; end else begin if (div_50 == TIMECONST_49) begin div_50 <= 6'b000000; en_50 <= 1'b1; end else begin div_50 <= div_50 + 6'b1; en_50 <= 1'b0; end end end always @ (posedge clk or negedge rst_n) begin if (!rst_n) begin clk_o <= 1'b0; end else if (en_50) clk_o <= ~clk_o; end endmodule

--- Quote Start --- In accordance with your post, I wrote the following code,could tell me is it right?is it the enable clock divider? THX very much. module divider (clk, rst_n, clk_o); parameter TIMECONST_49 = 6'b110001; input clk; input rst_n; output reg clk_o; reg [5:0] div_50; reg en_50; always @ (posedge clk or negedge rst_n) begin if (!rst_n) begin div_50 <= 6'b000000; en_50 <= 1'b0; end else begin if (div_50 == TIMECONST_49) begin div_50 <= 6'b000000; en_50 <= 1'b1; end else begin div_50 <= div_50 + 6'b1; en_50 <= 1'b0; end end end always @ (posedge clk or negedge rst_n) begin if (!rst_n) begin clk_o <= 1'b0; end else if (en_50) clk_o <= ~clk_o; end endmodule --- Quote End --- Hi simplorer, the signal is intended to be used as enable for for the FF's. e.g: always @(posedge clk) begin if (enable) ff_sig <= in; end

Hi, yes indeed, every FF is to be clocked by the 50MHz as usual but every FF meant to run at 1MHz needs the enable signal as well. This enable signal in a good compiler should be wired up to the enable port of the FF.The compiler infers that from the location of the signal construct(not its name!, you may even insert your construct directly instead of explicit signal). There are also certain pitfalls when using enable. In particular be careful about the logic level of any signal when enable is inactive, you may have to freeze it or deactivate it depending on the design. It is well-known that cascaded enable in multi-module systems is prone to bugs and needs extra care. But overall, it is excellent from timing perspective, though some may argue that it means more power. Kaz

--- Quote Start --- Hi, yes indeed, every FF is to be clocked by the 50MHz as usual but every FF meant to run at 1MHz needs the enable signal as well. This enable signal in a good compiler should be wired up to the enable port of the FF.The compiler infers that from the location of the signal construct(not its name!, you may even insert your construct directly instead of explicit signal). There are also certain pitfalls when using enable. In particular be careful about the logic level of any signal when enable is inactive, you may have to freeze it or deactivate it depending on the design. It is well-known that cascaded enable in multi-module systems is prone to bugs and needs extra care. But overall, it is excellent from timing perspective, though some may argue that it means more power. Kaz --- Quote End --- hi,Kaz,thx.I come from china and my english is poor,so i can not understand you completely,could you post some codes using verilog,even very simply, i think the code is the best language that we can kown each other&#12290; thank again&#65281;

the clock divider with enable using verilog

12 Replies

Altera_Forum
Honored Contributor
18 years ago
--- Quote Start ---
Hi,

use a counter running continuously on your 50MHz clk from 0 to 49 and back.
generate a single enable pulse when count say = 49. Enable should be low otherwise. Then use this enable pulse together with your 50MHz clk to enable your work at 1MHz.

Additionally, you may add a multicycle of 50 to your logic timing constraints since the required speed is now just 1MHz. Obviously, you don't need to do this if your design doesn't violate the 50MHz.

Regards
kaz
--- Quote End ---

In accordance with your post, I wrote the following code,could tell me is it right?is it the enable clock divider? THX very much.

module divider
(clk,
rst_n,
clk_o);

parameter TIMECONST_49 = 6'b110001;

input clk;
input rst_n;

output reg clk_o;

reg [5:0] div_50;
reg en_50;

always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
div_50 <= 6'b000000;
en_50 <= 1'b0;
end
else
begin
if (div_50 == TIMECONST_49)
begin
div_50 <= 6'b000000;
en_50 <= 1'b1;
end
else
begin
div_50 <= div_50 + 6'b1;
en_50 <= 1'b0;
end
end
end

always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
clk_o <= 1'b0;
end
else if (en_50)
clk_o <= ~clk_o;
end

endmodule
Altera_Forum
Honored Contributor
18 years ago
Hi,

use a counter running continuously on your 50MHz clk from 0 to 49 and back.
generate a single enable pulse when count say = 49. Enable should be low otherwise. Then use this enable pulse together with your 50MHz clk to enable your work at 1MHz.

Additionally, you may add a multicycle of 50 to your logic timing constraints since the required speed is now just 1MHz. Obviously, you don't need to do this if your design doesn't violate the 50MHz.

Regards
kaz

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the clock divider with enable using verilog

12 Replies

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