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Honored Contributor
Honored Contributorthe clock divider with enable using verilog
i am working with EPM570T100I5,which has no PLL,i want to get a 1MHz clcok,the global clock is 50MHz.i have read the posts about clcok divider,the enable clock is a good way,but i am a newbie,i didno...
Altera_ForumHonored Contributor
Honored ContributorHi,
use a counter running continuously on your 50MHz clk from 0 to 49 and back. generate a single enable pulse when count say = 49. Enable should be low otherwise. Then use this enable pulse together with your 50MHz clk to enable your work at 1MHz. Additionally, you may add a multicycle of 50 to your logic timing constraints since the required speed is now just 1MHz. Obviously, you don't need to do this if your design doesn't violate the 50MHz. Regards kaz
