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Hi,
use a counter running continuously on your 50MHz clk from 0 to 49 and back.
generate a single enable pulse when count say = 49. Enable should be low otherwise. Then use this enable pulse together with your 50MHz clk to enable your work at 1MHz.
Additionally, you may add a multicycle of 50 to your logic timing constraints since the required speed is now just 1MHz. Obviously, you don't need to do this if your design doesn't violate the 50MHz.
Regards
kaz
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In accordance with your post, I wrote the following code,could tell me is it right?is it the enable clock divider? THX very much.
module divider
(clk,
rst_n,
clk_o);
parameter TIMECONST_49 = 6'b110001;
input clk;
input rst_n;
output reg clk_o;
reg [5:0] div_50;
reg en_50;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
div_50 <= 6'b000000;
en_50 <= 1'b0;
end
else
begin
if (div_50 == TIMECONST_49)
begin
div_50 <= 6'b000000;
en_50 <= 1'b1;
end
else
begin
div_50 <= div_50 + 6'b1;
en_50 <= 1'b0;
end
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
clk_o <= 1'b0;
end
else if (en_50)
clk_o <= ~clk_o;
end
endmodule
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