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Altera_Forum
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17 years ago

the clock divider with enable using verilog

i am working with EPM570T100I5,which has no PLL,i want to get a 1MHz clcok,the global clock is 50MHz.i have read the posts about clcok divider,the enable clock is a good way,but i am a newbie,i didno...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi simplora,

You will always get some delay that is made up of:

- input pin to gate(routing)

- gate delay

- gate to output pin(routing).

The delay varies from device to device and by the way cplds are very fast in this respect because FPGAs have too much of routing garbage. Moreover, the fpga doesn't actually use simple AND gate but a LUT??

Kaz