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H simplora,
try the code below
as to pin-t0-pin delay. This is natural and is defined as the delay of combinatorial elements from an input pin to output pin. It is not much relevant in your case as you are not going to use clk_o as an external pin...
-- prbs generator
library IEEE;
use IEEE.std_logic_1164.all;
entity prbs_generator is
port(
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
data : out std_logic_vector(23 downto 0)
);
end entity prbs_generator;
architecture rtl of prbs_generator is
signal shift_reg : std_logic_vector(33 downto 1);
begin
process(reset, clk)
begin
if(reset = '1')then
shift_reg <= '0' & x"28EA5CB1"; -- seed value
data <= (others => '0');
elsif(rising_edge(clk))then
if(enable = '1')then
-- prbs generator
shift_reg(1) <= shift_reg(33) xor shift_reg(20);
shift_reg(33 downto 2) <= shift_reg(32 downto 1);
-- output
data <= shift_reg(24 downto 1);
end if;
end if;
end process;
end architecture rtl;
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thx again.i code s simple AND gate,like: out1 = in1 & in2,i found the out1 is delay about 6ns to in1 and in2,how to explain this.
Honored Contributor
