the clock divider with enable using verilog

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Hi simplora(nee ha),

I believe your counter code is correct.

As to enable, the code from pletz explains it well for the given assignment.

I am sorry I haven't use verilog for quite sometime(I used it in 2004/006 and can't remeber...). I know vhdl more than my mother language. If you wish I can do that in vhdl...

regards

Kaz

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hi,i do not know the VHDL,but i can compiler the VHDL code,and i think the RTL is simple,so please post some VHDL code which can be compilered,and another question:

how can i understand "pin to pin delay", i compiler the code i posted above,and do the time simulation,i find the delay is about 12ns between

clock rising edge and the clk_o,i don't know where the delay comes from?

THX!