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Altera_Forum
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17 years ago

the clock divider with enable using verilog

i am working with EPM570T100I5,which has no PLL,i want to get a 1MHz clcok,the global clock is 50MHz.i have read the posts about clcok divider,the enable clock is a good way,but i am a newbie,i didno...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Hi simplora(nee ha),

I believe your counter code is correct.

As to enable, the code from pletz explains it well for the given assignment.

I am sorry I haven't use verilog for quite sometime(I used it in 2004/006 and can't remeber...). I know vhdl more than my mother language. If you wish I can do that in vhdl...

regards

Kaz