--- Quote Start ---
In accordance with your post, I wrote the following code,could tell me is it right?is it the enable clock divider? THX very much.
module divider
(clk,
rst_n,
clk_o);
parameter TIMECONST_49 = 6'b110001;
input clk;
input rst_n;
output reg clk_o;
reg [5:0] div_50;
reg en_50;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
div_50 <= 6'b000000;
en_50 <= 1'b0;
end
else
begin
if (div_50 == TIMECONST_49)
begin
div_50 <= 6'b000000;
en_50 <= 1'b1;
end
else
begin
div_50 <= div_50 + 6'b1;
en_50 <= 1'b0;
end
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
clk_o <= 1'b0;
end
else if (en_50)
clk_o <= ~clk_o;
end
endmodule
--- Quote End ---
Hi simplorer,
the signal is intended to be used as enable for for the FF's.
e.g:
always @(posedge clk) begin
if (enable) ff_sig <= in;
end
Honored Contributor
