Testing AXI custom component

This post is now 6 years old. Just out of curiosity, does Intel actually plan to obsolete the ARM based SoCs? I do not understand what else they could use when Microsemi and Xilinx also use ARM. If ARM is present, AMBA buses will be required as well. Also, as far as I am aware, the AXI BFM is present in Quartus Prime by default.

This old post has confused me.

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How about here:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0534b/babidbde.html

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That's definitely them. They've removed a couple of them (APB, AHB). Thanks Tricky!

Hello tricky,

I have invested a lot of time porting my designs to AXI. I am very sorry to hear this.

I always have used some self-written procedures to test my AXI components.

I have visited link but i haven't found "axi verification components", where do you have downloaded it?

Thanks

Altera doesn't really want to use axi. Axi is only really used by the arm subsystems and altera never really get much traction with it. And now being owned by Intel, arm SOCs will be dropped. Everything altera is Avalon and will remain so for a long time.

You can download axi verification components for free from the arm website.

https://www.arm.com/products/system-ip/amba-specifications

If you have an expensive formal tool, you can verify your custom component against that, but if you can't afford the $50k for a licence, you can at least use it to test your custom component and home made axi bfm.

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I have seen that the bridge between the axi component instantiated into qsys and the hps is very verbose! There are many componets auto-instantiated by qsys like a axi-avalon translator or something like that, did you try just to connect you component directly to the hps without using the qsys generated code? In other words have you tried just to instantiate in qsys the hps and outside the tool link it to your component?

I will try for sure to debug it with signal tap! That is always a good idea.

The verification environment provided as bfm in the quartus 15.1 and quartus 16.0 is not so straight forward to use, do you know what they mean for read/write and combined accepted capability?

Thank you for any tips,

Cheers. =)

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In short: No. I needed a working system in too short a time frame to continue debugging. If I was designing now, I'd connect the HPS directly to any of my AXI components, and maybe even license an ARM switch IP instead of using Avalon to handle multiple components. My IP wasn't setup to handle TIDs correctly, and we switched to using the simpler Avalon bus architecture, so this became a non-issue for us. In addition, there's no multi-AXI command handling built in to the Linux kernel driver, so there is only one transaction active from the HPS to the fabric at any given point either way (I believe through communication with Altera).

Not to mention that if you lose the FPGA clock and the AXI gets stuck, an HPS running Linux will freeze until an AXI transaction completes (this is part of AXI). Maybe adding a timeout that can reset the AXI bus could work.

I have seen that the bridge between the axi component instantiated into qsys and the hps is very verbose! There are many componets auto-instantiated by qsys like a axi-avalon translator or something like that, did you try just to connect you component directly to the hps without using the qsys generated code? In other words have you tried just to instantiate in qsys the hps and outside the tool link it to your component?

I will try for sure to debug it with signal tap! That is always a good idea.

The verification environment provided as bfm in the quartus 15.1 and quartus 16.0 is not so straight forward to use, do you know what they mean for read/write and combined accepted capability?

Thank you for any tips,

Cheers. =)

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Hi Derim,

Did you get any solution?

I am working on a AXI custom components too, it works if for each transaction I use the "handshake" between the master and the slave with the valid and ready signals, but when I use the burst transaction everything stops work. I thought that I am facing problems related to the clock signal, but after what you have said in the previous post it seems that the problems are more and they cannot be found just in the manual.

Any tips is welcome.

Cheers.

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I'd suggest a project with just the HPS and your component, and then hammer on it using SignalTap. Burst is more complicated, so my first question is always going to be whether or not your AXI component works correctly-- ARM offers UVM files to verify proper function that you can use to test your component. Otherwise, I'd say you're going to need to instrument it and look at where things are getting held up. Testbenching and simulation work wonders, if you have the time to spend on that as well.

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I currently have a ticket in with Altera. I'll post whatever I hear in the forum once I get a response.

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Hi Derim,

Did you get any solution?

I am working on a AXI custom components too, it works if for each transaction I use the "handshake" between the master and the slave with the valid and ready signals, but when I use the burst transaction everything stops work. I thought that I am facing problems related to the clock signal, but after what you have said in the previous post it seems that the problems are more and they cannot be found just in the manual.

Any tips is welcome.

Cheers.