Forum Discussion
Altera_Forum
Honored Contributor
9 years agoI have seen that the bridge between the axi component instantiated into qsys and the hps is very verbose! There are many componets auto-instantiated by qsys like a axi-avalon translator or something like that, did you try just to connect you component directly to the hps without using the qsys generated code? In other words have you tried just to instantiate in qsys the hps and outside the tool link it to your component?
I will try for sure to debug it with signal tap! That is always a good idea. The verification environment provided as bfm in the quartus 15.1 and quartus 16.0 is not so straight forward to use, do you know what they mean for read/write and combined accepted capability? Thank you for any tips, Cheers. =)