Altera_ForumHonored Contributor15 years agoTestbench: Read from Text File I have a set of test patterns in text file to be used in test bench written in verilog. test pattern will be sent to top module one by one for every posedge of clock once the ena is high. Is t...Show More
Recent DiscussionsLooking for the Document ID 854068Suggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.Error (209014): CONF_DONE pin failed to go high in device 1.