Forum Discussion
Honored Contributortest with massive data
Recently I'm writing a decoding module, which needs massive data for accuracy testing. However, inputing these data manually and putting them in the testbench file seems incredible, so I wonder whether there is some kind of software to generate this file or some other method. :)
8 Replies
Altera_ForumMany ways are possible, it depends if you only need to simulate your code or you also need to watch it running on the hardware in real-time.
- Altera_Forum
Well it's nearly the same in Verilog. You can define a huge RAM in the testbench and fill it on simulation begin with the readmem task from a file.
- Altera_Forum
I have successfully used textio to do a relatively simpler job. But it seems that the textio testbench can only be written in VHDL, not verilog. Is that so?
- Altera_Forum
I forgot to tell you that the Megafunction is the ALTSYNCRAM
:) - Altera_Forum
Still you did not exactly told the quantity of data, but you may check if the RAM capacity of your FPGA is enough for your needs. In that case, you may instantiate a RAM block (with enough size) and use it as a ROM (in the MegaWizard procedure you are asked if you want to use it as a ROM and initialize its cells with a numerical file that you can edit).
Hope this helps. - Altera_Forum
I mean the quantity of data.
I heard that maybe using RAM can store the test data, just don't know how to do that. - Altera_Forum
Furthermore, nearly any thinkable generation algorithm could be coded in HDL as well.
- Altera_Forum
Hi,
Not sure what you mean by "massive data". Are you refering to a large quantity of numeric data or a particular type of data? You could write a testbench that accesses your "masive data" files (Assuming you have the massive data in some kind of data file!). VHDL provides a textio package that allows the testbench to access files. Although it has limited functionality, you may be able to write a testbench to parse the file into the form you require. If not then maybe a bit of C/Perl etc preprocessing to make the file easier to handle in VHDL might be beneficial.
