Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributortest with massive data
Recently I'm writing a decoding module, which needs massive data for accuracy testing. However, inputing these data manually and putting them in the testbench file seems incredible, so I wonder whet...
Altera_ForumHonored Contributor
Honored ContributorWell it's nearly the same in Verilog. You can define a huge RAM in the testbench and fill it on simulation begin with the readmem task from a file.
