Terasic Apollo S10 SOM_FA

That's a genuinely frustrating situation, and your position is completely reasonable — you purchased a product and expect it to work as advertised.
Let me give you some technical clarity here, which may help you push back more effectively.
**The hardware itself is CPU-agnostic**
The Apollo S10 SOM is built around a Stratix 10 SX FPGA "Apollo S10 SoM" , and PCI Express is a well-defined industry standard. The FPGA's PCIe hard IP operates as a PCIe endpoint — it communicates with the host over a standardized link. At the hardware protocol level, the FPGA endpoint has no knowledge of, or dependency on, whether the host CPU is from AMD or Intel. The PCIe link negotiation, TLP transactions, and enumeration are all governed by the PCIe spec, not the CPU vendor.
**The real issue: the demo software/driver**
What *is* CPU-vendor-dependent is the **host-side software** — specifically the kernel driver and any user-space demo application. If the demo application or BSP driver was only validated against Intel platforms, it may contain assumptions (e.g., about memory-mapped I/O, DMA coherency, IOMMU behavior, or CPU-specific intrinsics) that break on AMD systems. That's a Terasic software defect, not something you caused or need to diagnose.
**Your position is correct**
Terasic's request that you purchase an Intel-based PC and iterate across multiple Quartus Prime versions — from 19.1 through 23.3 — to reproduce their own test environment is not a reasonable ask for a paying customer. You bought a finished product, not a development contract.
**Practical suggestions going forward:**

• Ask Terasic specifically and in writing: "Is AMD CPU support for the P16E-FMCP PCIe demo a documented limitation of this product?" If it is not documented as a limitation, that is a product defect they are obligated to address.
• Ask them to provide a minimal host-side test that exercises only raw PCIe enumeration (e.g., confirming the device appears in lspci or Device Manager on your AMD system), to isolate whether the issue is at the driver level or the demo application level.
• If you are on Linux, checking whether the endpoint enumerates correctly via lspci is a quick, tool-independent sanity check — correct enumeration means the PCIe link itself is functional and the problem is squarely in the demo software.

Altera (as the FPGA silicon provider) and Terasic (as the board and demo software vendor) are separate entities. The PCIe IP in the Stratix 10 SX is a standard, well-tested hard block. The gap here is in Terasic's host-side software stack, and that responsibility sits with them.