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Altera_Forum's avatar
Altera_Forum
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12 years ago

Temperature and timing problem

Hello

I have Cyclone II FPGA EP2C5F256I8N in a design clocked with a 50MHz oscilator and at startup the FPGA reads a config from an external EEPROM. I have done power up and environmental tests and there seems to be a problem related to cold temperature, but only at startup. When decreasing the temperature below 0 degrees celsius my module goes to fatal immediately when I do a cold start. The fatal log indicating the FPGA not being ready within timeout limits, ie config_done and init_done are not set.

After some measuring with oscilloscope I have found out that the delay from VCC goes high to the code starts downloading from EEPROM to the FPGA is varying with temperature. As the temperature decreases this delay increases greatly, to several seconds at 0 degrees celsius.

I will continue measuring control signals between CPU and FPGA to see if the CPU does something funny at low temperatures. I just wanted to bring up the problem here to if you guys have any good ideas.

As this hardware is already deployed in field in great numbers I am very eager to find a solution to this problem

Best regards

Holger

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You don't say what programming mechanism the FPGA employs to boot it. You mention an EEPROM - can I assume Active Serial (AS) configuration?

    Assuming AS configuration, the clock used comes from the FPGA (not the 50MHz oscillator you mention). This FPGA sourced clock is a fairly crude and inaccurate, with 100% variation - i.e. for normal AS boot (20MHz) this clock can be anywhere from 10MHz to 20MHz. This tells us something about how it's generated and it's not surprising that it slows down with temperature, although I can't find anything specific that identifies exactly how. Refer to the configuration handbook (http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf).

    You mention a 50MHz oscillator and CPU. Although the 50MHz oscillator won't come into play if AS config is employed, it could if any passive configuration scheme is (such as Passive Serial (PS) configuration). In this case, if the oscillator is causing the problem, you should be able to specifically see this clock suffering with temperature - most likely loosing amplitude or stopping, rather than slowing.

    Have you ever seen it completely fail to boot? I acknowledge you've specified an industrially rated part. Perhaps Altera still qualify it as that if boot time is significantly reduced. This may be something you simply have to accommodate. You mention a timeout - sounds like it'll have to be increased.

    I'd suggest this is worth raising a support case with Altera.

    Regards,

    Alex