Temperature and timing problem

You don't say what programming mechanism the FPGA employs to boot it. You mention an EEPROM - can I assume Active Serial (AS) configuration?

Assuming AS configuration, the clock used comes from the FPGA (not the 50MHz oscillator you mention). This FPGA sourced clock is a fairly crude and inaccurate, with 100% variation - i.e. for normal AS boot (20MHz) this clock can be anywhere from 10MHz to 20MHz. This tells us something about how it's generated and it's not surprising that it slows down with temperature, although I can't find anything specific that identifies exactly how. Refer to the configuration handbook (http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf).

You mention a 50MHz oscillator and CPU. Although the 50MHz oscillator won't come into play if AS config is employed, it could if any passive configuration scheme is (such as Passive Serial (PS) configuration). In this case, if the oscillator is causing the problem, you should be able to specifically see this clock suffering with temperature - most likely loosing amplitude or stopping, rather than slowing.

Have you ever seen it completely fail to boot? I acknowledge you've specified an industrially rated part. Perhaps Altera still qualify it as that if boot time is significantly reduced. This may be something you simply have to accommodate. You mention a timeout - sounds like it'll have to be increased.

I'd suggest this is worth raising a support case with Altera.

Regards,

Alex