New ContributorNew quartus prime user here.
Is it possible to use 625mhz clock input in max10 fpga?
Below is the screenshot of the compilation report where I'm getting warning under Timing analyzer.
Can anyone explain what the warning is and how to correct it.
Frequent ContributorHi Saranya
Thanks for your inquiry. Referring to Table 27 in doc below
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf
The max Fin supported is 472.5MHz, can you try if that resolve the issue? I am curious if you are using PLL?
Thanks.
Eng Wei
Frequent ContributorHi Saranya
We do not receive any response from you to the previous reply that we have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Thanks.
Eng Wei
