TCP Ethernet packet in FPGA?

ghertz,

What you are trying to do has a steep learning curve (but you have to start somewhere). I believe the kit you have comes with an example design in FLASH that they call "Board Update Portal". It should have the source code which is a good place to start.

The board has a Marvell 88E1111 Ethernet Phy. The Phy is the interface between the physical cable and the digital parts of Ethernet (Layer 1 of OSI model). Inside the FPGA, you need to create an Ethernet MAC (Layer 2) that interfaces between the Phy and higher software layers. Altera provides the "Triple-Speed Ethernet" IP core for that purpose (ie TSE core). The first thing you have to do is create the TSE core with your desired options, instantiate it in your design. The signals in your EMAC that communicate with the Phy will be brought out to your top level design. Which ones depend on which Phy protocol you choose. There are many (MII, GMII ....). Like I said, there is a bit of a learning curve.

You will then need code to initialize the EMAC and Phy. At that point, you can send packets from your PC and should see data come out in SignalTap. Normally, there would be software that interfaces to the EMAC (eg TCP/IP etc).

It's almost impossible to do all this without and example, but the board comes with one.

Normally, it is wise to read datasheets in detail, which you should do for the TSE. Unfortunately, Marvell makes it difficult to obtain their datasheets and you would be wise to find a board with a different Phy if possible.