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Altera_Forum
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16 years ago

System verilog (general info)

quartus9.1 support SystemVerilog, does anyone know how the SystemVerilog assertions are processed when synthesisin Thanks in advance for helping, Best regards Jenny teh
Altera_Forum's avatar
Altera_Forum
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16 years ago

You may check this out: Quartus II Support for SystemVerilog 2005 in Help file Section 17