Occasional Contributor
Occasional ContributorHi Wincent,
The device is a Agilex5 development kit from macnica, a Japanese company.
I use a design example from IP Catalog, and map the pin to the macanica Agilex5 devkit.
In the signal tap, ltssm stucks at 0, and p0_pin_perst_n is 0 too.
I try to modify PCIE spread sprectrum in BIOS, but haven't found this setting in current main board. I will change another main board and try again, and update to you if any news. FvM Wincent_Altera
BTW, Is there any difference for downloading .sof and using .jic file for FPGA PCIE debug? Should I only use .jic then re-power the whole system?
Please let me know if you have any more syggestions.
Regards.
Regular ContributorHi SYiwe ,
If you are using .sof file, you may need to perform host reboot to get the PCIe link enumerate.
I had created before an document for PCIe Getting Started , you may refer the document in link below
Although it is for Agilex 7, but the overall step shall be the identify.
https://community.altera.com/discussions/ip-and-transceiver/how-to-run-pcie-gen-5-design-example-using-altera-fpga-device/125814
In the signal tap, ltssm stucks at 0, and p0_pin_perst_n is 0 too.
>> Can you show me the signal ? A printscreen will do.
Regards,
Wincent
Occasional ContributorHi Wincent,
I change another main board, now system PLL can lock, but both p0_pin_perst_n and ltssm stuck at 0,
here's the screenshoot. Any suggestions? Should I focus on the RC since perst_n is output from RC? Regards.
