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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
15 days ago

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Hi all, The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge. Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven fr...
Programmable Logic Device
SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
4 days ago

Hi Wincent，

Thank you for your reply, wish you happ new year.

  1. The design is a full compiled Agilex5 PCIE example design,
  2. A signal tap is instanced and I found the system PLL cannot be locked with signal tap,
  3. I've used lspci and no FPGA PCIE EP found,
  4. Please let me know if you have any more suggestions. 

 

Regards.

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 days ago

Hi SYiwe ,

Which device that you are using ? 
Agilex 5 Modular devkit ? IF yes, I would suggest to try out the design example from IP Catalog.

A signal tap is instanced and I found the system PLL cannot be locked with signal tap,
>> Do you capturing the ltssm signal ? 
>> What is the ltssm status ?

At the meantime, you may try out the suggestion provided by our community expert FVM as mentioned above

Regards,
Wincent_Altera

  • SYiwe's avatar
    SYiwe
    Icon for Occasional Contributor rankOccasional Contributor
    2 days ago

    Hi Wincent,

    The device is a Agilex5 development kit from macnica, a Japanese company.

    I use a design example from IP Catalog, and map the pin to the macanica Agilex5 devkit.

    In the signal tap, ltssm stucks at 0, and p0_pin_perst_n is 0 too.

    I try to modify PCIE spread sprectrum in BIOS, but haven't found this setting in current main board. I will change another main board and try again, and update to you if any news. FvM​ Wincent_Altera​ 

    BTW, Is there any difference for downloading .sof and using .jic file for FPGA PCIE debug? Should I only use .jic then re-power the whole system?

    Please let me know if you have any more syggestions.

    Regards.

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      2 days ago

      Hi SYiwe​ ,

      If you are using .sof file, you may need to perform host reboot to get the PCIe link enumerate.
      I had created before an document for PCIe Getting Started , you may refer the document in link below
      Although it is for Agilex 7, but the overall step shall be the identify.

      https://community.altera.com/discussions/ip-and-transceiver/how-to-run-pcie-gen-5-design-example-using-altera-fpga-device/125814

      In the signal tap, ltssm stucks at 0, and p0_pin_perst_n is 0 too.
      >> Can you show me the signal ? A printscreen will do.

      Regards,
      Wincent

      • SYiwe's avatar
        SYiwe
        Icon for Occasional Contributor rankOccasional Contributor
        1 day ago

        Hi Wincent,

        I change another main board, now system PLL can lock, but both p0_pin_perst_n and ltssm stuck at 0,

        here's the screenshoot. Any suggestions? Should I focus on the RC since perst_n is output from RC? Regards.