system design using cyclone II

Hi Allison,

Please see the attached m-file for an example of how you would decimate an input signal sampled at 4MHz to 8-bits, to 4kHz at 10-bits. The decimation sequence consists of a CIC filter that decimates the signal by 250, and then a Nyquist filter that decimates by 4 (this could also be implemented as a cascade of two half-band filters).

The passband droop due to the CIC filter is not very large. Since you only want to detect the DC value (the demodulated sinusoid amplitude), I don't think you need to use a compensation FIR. You do want a combination of CIC plus FIR, but the FIR filter(s) are just used for the final decimation stages.

Since the final FIR stages are operating at low clock rates, the 'optimal' implementation will depend on how Altera's FIR Compiler II implements time-demultiplexing (folding, or logic reuse). Run a few test designs through FIR Compiler II and see how well they work.

NOTE: The final FIR decimation stage filter design is probably sub-optimal, in that the filter has a much faster transition edge than your application probably requires. For example, you could design an FIR filter with a slow transition from DC to the stop-band edge that will require fewer coefficients, and would not affect the DC measurement. However, assuming the FPGA is running at say 40MHz, and processing 16kHz samples, there is an oversampling ratio of 2500, so 'sub-optimal' may in fact be fine, given that the FPGA could use 1 multiplier and 2500 clocks to implement the FIR filter(s).

Cheers,

Dave