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Altera_Forum
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14 years ago

system design using cyclone II

Hi, I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi Dave,

I have finished my MATLAB model of the lock-in amplifier and tested on the training data. It works greatly. Thank you very much for your kindly help!!

Now I am facing the challenge of implementing the amplifier in FPGA (which I assume is much harder than the previous work...). Since the lock-in amp consists of PLL, NCO, mixer and filter. I used the megacore function to generate each part.

The design of filter is a little bit confusing. I need to design a CIC filter followed by a compensation FIL filter. In my case, the sampling frequency is 4Mhz, the frequency of interest is 154khz, the passband width is 1khz. So I probably need a bigger downsamping factor, I set it to 128.

The CIC parameters:

input signal datapath 16bit, R=128, N=9, M=1, full precision data length is 16+N*log2(R*M)=16+9*7=79bit. Since I want 16bit output, the megafunction uses Hogenauer pruning technique to reduce the data widths.

The FIR design:

Megafuncton would generate a matlab file that can generate a compensation filter. The coefficients would be loaded into QuartusII and generate the FIR filter.

Am I on the right track?

Allison