--- Quote Start ---
I did what you suggested and modeled the lock-in amplifier in matlab (floating & fixed point). The results of both are the same =).
--- Quote End ---
Great!
--- Quote Start ---
but I found several problems which I didn't expect before.
--- Quote End ---
Which is why modeling is a good way to start :)
--- Quote Start ---
1st, 40MSPS is too high to design a good LPF if my frequency of interest is 154khz. so I adjusted the sampling frequency to 4MSPS.
--- Quote End ---
Why is it too fast? You need to keep in mind that the input bandwidth to the ADC needs to be consistent with its sample rate. So if your ADC is designed to operate at 40MHz and it has an input filter with 20MHz of bandwidth, regardless of what clock rate you operate it at, it will be letting in 20MHz worth of noise. To eliminate that noise, you can either change the filter and the sample rate, or you can sample at 40MHz and then use digital decimation filters.
--- Quote Start ---
2nd, the paper& slides are very helpful, thanks! but i got a lil confused about the Q0.N representation. The product of two Q0.N (actual bit is 1+0+N=N+1) number is Q0.2N (1+0+2N)? maybe it actually means Q1.2N, there are 1 signed bit, 1 bit for whole and 2N bit for fractions.
--- Quote End ---
Qm.n representation is always signed, so there is 1-bit used for the sign, and the rest for the m and n bits, eg., a B-bit binary value can be used to a Q0.(B-1) number. The largest magnitude signed value is the most negative, eg. for an 8-bit Q0.7 value, it is the signed binary value -128, or -1.0 fractional integer. The largest product of two Q0.7 is -1 x -1 = +1, so that requires a Q1.x representation, i.e., Q0.7 x Q0.7 = Q1.14. Another way to look at it, is that an 8-bit product requires 16-bits to represent, which could potentially mean that you can use Q0.15, but because of the -1 x -1 = +1 product, the representation of the product is actually Q1.14.
If you use signed-symmetric format, where the -1.0 terms are replaced with the next most-negative value, -1.0 + 1/2^B, which is the negative of the most positive value, then the -1.0 x -1.0 = 1.0 product never occurs. The product of two Q0.7 numbers is still Q1.14 format, but you can discard the MSB (not the sign bit, but the next bit) after the product is calculated, since that bit is never set, or you can perform a multiply-add, without being concerned about the add operation causing an overflow of the MSB.
--- Quote Start ---
3rd, after convolution, besides LSBs, I also need to cut some MSBs too right ?
--- Quote End ---
It depends. If you never know what is being filtered, then you have to design for worst-case input signals. If you control the type of input signal and know what it should be (and monitor it in the hardware), then you can optimize for just the signals you expect. That is part of the modeling task :)
For example, will the sensors have amplifiers, so that the ADC input range is always driven over its full amplitude range, or will there be some minimum and maximum amplitude over which it operates? Systems with ADCs that have fewer bits will often be driven by automatic-gain control (AGC) amplifiers that keep the amplitude at the input to the ADC constant.
--- Quote Start ---
4th, I used fdatool in matlab for fixed point coeff. there is one option 'set quantized parameter' where I specify the bit width of input, coeff and output. but I still need to round the exported coeffs into fixed point integers right?
--- Quote End ---
I'm not sure about all the FDATool features. I usually just use it to calculate the filter floating-point coefficients, and then deal with the quantization of the coefficients myself.
--- Quote Start ---
I attach my matlab code here (only the fixed point), I explained every step I did in the comments. could you please take a look and tell me if I did right?
--- Quote End ---
Sure, I'll take a look.
Cheers,
Dave
Honored Contributor
