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Altera_Forum
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14 years ago --- Quote Start --- I am now implementing each block unit in quartusII... --- Quote End --- Its not a good idea to just use Quartus. You should first design your system, eg., using MATLAB or C-code; use floating-point numbers everywhere in one model (to get an end-to-end design of an ideal system), and then create a quantized (bit-accurate) model that matches your hardware design. In fact, its more of an iterative process. You need to first see what is available in Quartus, and then as you realize you need to understand things like bit-widths, go back to your software model and try different parameters to see how they affect your result. --- Quote Start --- 1. My input signal is 16bit, I made the NCO generate 16-bit cosine and sine wave. After mixer, I should have two modulated signals of 32bit width. --- Quote End --- After the multiplication you will have two 32-bit values, however, the dynamic range of those signals will not be 32-bits. If you plot a spectrum of the input signal (or a model of it), and a spectrum of the mixer complex-valued exponential (a single tone, with harmonics), the spectrum of the mixer output is the convolution of these two signals (since they are multiplied in the time domain). The number of bits to keep is determined by where the harmonics are in this spectrum. If you want 16-bits, you might actually have to use an 18-bit NCO output value. To start with, convergent round the mixer output to 16-bits. (See the links below for an NCO example) --- Quote Start --- Now, I keep the datapath as 32bit, and input each multiplied result into a low-pass FIR filter(developed through megafunction FIR compiler, single rate, coefficients 8bit width). Should I keep the full precision, which is 40bit length, or should I truncate MSB/LSB? --- Quote End --- The number of bits to preserve depends on your signal power and the dynamic range you wish to preserve. Your filter will be coherently integrating the received sinusoid. You need to model this first to understand how the signal amplitude increases with longer filters. Note that since you only need very narrowband filters, FIR compiler might not be your best filter type. It might be better with a combination of a CIC filter and FIR filters. For now though, just gain an understanding of how the system will plug together by starting with an FIR filter. --- Quote Start --- from what I learnt before, the ADC has a Vref=+-2V, 16bit, then the signed fractional representation of the sampled data is (3.13), including the signed bit. I guess from NCO, the cosine & sine wave is (1.15), so after mixer it is (4.28). And after FIR the full precision is 42bit, I can keep the first 16bit if my output resolution is 16bit. right? --- Quote End --- The numeric format of the input is whatever you decide it is; if your ADC input is Vpp = 2*Vp, and you conceptually normalize the input by Vp, then the input range is -1.0 to 1.0. In 16-bit format, this can be Q0.15 (sign bit and 15-bits of fraction). A 16-bit NCO output is Q0.15. The FIR filter output will depend on the number of taps. Take a look at these slides, paper, and code examples: http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip) Page 39 of the PDF (p38 of the slides) has an FIR filter showing input bit-widths and how they grow through the filter. p137 shows the filter again, with different parameters (the code is in the zip file). Page 80 of the PDF (p88 of the slides) shows the spectrum of a mixer output. Note how the harmonics produce alias images. The bit width of your NCO needs to be defined to keep these alias images below the quantization noise floor of the final output bit-width. --- Quote Start --- 2. The filtered result will be squared and summed and take the root. How can I decided the bit length then? --- Quote End --- I don't think you need to do that on the FPGA. Your filter will output averaged data every second or so. You need the data from all sensors to calculate a position, so start by reading them out using a processor or to MATLAB, convert the integer valued filter outputs floating-point, convert them to currents using whatever calibration scheme you come up with, and then calculate the position. Cheers, Dave