Forum Discussion
Occasional ContributorSynthesis results and different behavior
1) Yes. There are many VHDL attributes like this. Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html
2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.
3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.
Super ContributorFix the clock everywhere and then try it out to see if it works. If it doesn't, reply back with what is still not working. You should also include warning messages you get which can help clue you in to the issues in your design.
Occasional ContributorThank you for your comment.
As a result of correcting all sources, it was confirmed that it works normally.
Thank you very much for your detailed answer.
