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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Synthesis results and different behavior

I made an SPI interface circuit, but the SCLK output is always 'H' and it doesn't work. It would be helpful if you could give me some hint to solve it. The survey results are as follows. 1) MOSI...
  • sstrell's avatar
    sstrell
    3 years ago

    1) Yes. There are many VHDL attributes like this. Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html

    2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.

    3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. we are now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding. If you have any further questions or concerns, please don't hesitate to let us know. Thank you for reaching out to us!


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